The present invention relates generally to dielectrics for field effect semiconductor devices, and more particularly to dielectrics that may retain charge for nonvolatile insulated gate field effect transistors.
As is well known, semiconductor devices can include insulated gate field effect transistor (IGFET) type devices. IGFET-type devices typically include a transistor gate separated from a channel region by a dielectric. A potential applied to a gate can then be varied to alter channel conductivity.
While many IGFET type devices are volatile (e.g., conventional metal-oxide-semiconductor FETs), nonvolatile devices may also include IGFET-like approaches. Nonvolatile IGFET-like devices typically retain electric charge through one or more methods (e.g., storing, trapping charge). One conventional nonvolatile device can be a floating gate electrically erasable programmable read only memory (EEPROM). A floating gate EEPROM can include a floating gate electrode situated between a control gate and a channel. Charge, including electrons and/or xe2x80x9cholesxe2x80x9d, may be stored in a floating gate electrode. Such a charge may alter a threshold voltage of a resulting nonvolatile IGFET-type device. As will be noted below, a drawback to any floating gate device can be higher programming and/or erase voltages with respect to other nonvolatile approaches.
Another nonvolatile IGFET type device can include a dielectric interface to trap charge. For example, devices have been proposed that include a metal gate formed over a dielectric of silicon nitride and silicon dioxide. Such devices have been referred to as metal-nitride-oxide-semiconductor (MNOS) devices. A drawback to many MNOS devices has been lack of charge retention and/or uniformity of programming.
A third type of nonvolatile device may include one or more dielectric layers for storing charge. Such devices may be referred to generally as silicon-oxide-nitride-oxide-silicon (SONOS) type devices. One very basic type of SONOS device may include a polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) gate formed over a dielectric layer that includes a silicon nitride layer sandwiched between silicon dioxide layers.
SONOS devices can have lower programming voltages than other conventional nonvolatile devices, such as some types of floating gate devices. In addition, the SONOS fabrication process can be compatible with standard complementary metal oxide semiconductor (CMOS) process technology. To maintain this compatibility, SONOS devices may be scaled along with other transistors used in the process. The ability of SONOS devices to maintain performance and reliability as they are scaled can be an important feature.
To better understand the formation of SONOS devices, a conventional way of forming a SONOS device is set forth in FIGS. 9A, 9B, and 10A to 10F. FIG. 9A is a flowchart illustrating certain process steps involved in crating an integrated circuit containing SONOS devices. FIG. 9B is a side cross sectional view of a SONOS type device during a program operation. FIGS. 10A-10F set forth a number of side cross-sectional views of a portion of an integrated circuit containing SONOS devices following the various conventional process steps described in FIG. 9A.
The conventional process described in FIG. 9A is designated by the general reference character 900. A conventional process 900 may include the steps of growing a tunnel oxide (step 902) in a furnace. Subsequently, wafers that now include the tunnel oxide can be transferred from a furnace to a different machine for growing other layers in an ONO dielectric for a SONOS-type device. In FIG. 9A, such a step may include transferring wafers to a chemical vapor deposition (CVD) machine (step 904).
A conventional method 900 may further include depositing a silicon nitride layer over tunnel oxide in a CVD machine (step 906), depositing a top oxide layer over a nitride layer in the same or a different CVD machine (step 908), and depositing a polysilicon gate layer (step 910).
The above steps may form various layers for a SONOS-type device. Such layers can then be patterned to form a SONOS-type transistor. Patterning steps may include forming a gate mask (step 912), etching gate structures (step 914), and depositing and etching a spacer layer (step 916).
Referring to FIG. 10A, a side cross-sectional view of a portion of an integrated circuit prior to the beginning of a conventional process 900 is shown. An integrated circuit portion includes a substrate 1000, and may include isolation regions 1002 formed by prior process steps. As an example, isolation regions 1002 may be formed by various conventional isolation processes including but not limited to shallow trench isolation (STI) or the local oxidation of silicon (LOCOS).
It is noted that a substrate 1000 may also include various impurity regions, formed by ion implantation and/or other diffusion methods. As but a few examples, n-type wells may be formed in a p-type substrate (or vice versa), or p-type wells may be formed within n-type wells (or vice versa).
Referring again to FIG. 9A, a conventional process 900 may begin by growing a tunnel oxide (step 902) in a furnace. A portion of an integrated circuit following step 902 is set forth in FIG. 10A. Referring to FIG. 10A, a portion of an integrated circuit includes a tunnel oxide 1004 on a substrate 1000.
A conventional process 900 can continue by transferring a wafer from a furnace to a chemical vapor deposition (CVD) machine (step 904). A conventional process 900 can continue by depositing a silicon nitride layer in a CVD machine (step 906). A portion of an integrated circuit following step 906 is set forth in FIG. 10B. Referring to FIG. 10B, an integrated circuit may now be situated within a CVD machine, an integrated circuit portion can now include a nitride layer 1006 deposited over a tunnel oxide 1004. A nitride layer 1006 can conventionally include essentially only silicon nitride (Si3N4).
A conventional process 900 can continue by depositing a top oxide layer (step 908) in a chemical vapor deposition (CVD) machine. Referring to FIG. 10C, an example of a portion of an integrated circuit following step 908 is set forth. At this point, a tunnel oxide 1004, a nitride layer 1006 and a top oxide layer 1008 have been formed over a substrate 1000. A top oxide layer 1008 can be conventionally formed by chemical vapor deposition (CVD).
A conventional process 900 can continue by depositing a polysilicon gate layer (step 910). An example of a portion of an integrated circuit following a step 910 is set forth in FIG. 10D. Referring to FIG. 10D, a polysilicon gate layer 1010 has been deposited on a top oxide layer 1008. As also shown in FIG. 10D, a gate protection insulator 1012 may also be formed over polysilicon gate layer 1010.
At this point, in a conventional process 900, silicon-oxide-nitride-oxide-silicon (SONOS) layers can correspond to a substrate 1000, tunnel oxide 1004, nitride layer 1006, top oxide layer 1008, and polysilicon gate layer 1010, respectively.
A conventional process 900 may continue with lithography and etch steps to isolate and form SONOS devices. In conventional lithography, a gate mask may first be formed (step 912). An example of a portion of an integrated circuit following step 912 is set forth in FIG. 10E. A gate mask material 1014 can be deposited and patterned using any of various lithographic techniques. A gate mask material 1014 may generally include of a photoresist material.
Following the formation of a gate mask (step 912), gate structures can be etched (step 914). Referring now to FIG. 10F, a portion of an integrated circuit following step 912 is set forth. A suitable etching process can remove portions of the tunnel oxide 1004, nitride layer 1006, top oxide layer 1008, polysilicon gate layer 1010, and a gate protection insulator 1012 that are not covered by gate mask material 1014. In this manner, SONOS device gate structures 1016 can be formed on a substrate 1000.
A conventional process 900 can continue by depositing and etching a spacer layer (step 916). An example of a portion of an integrated circuit following step 916 is set forth in FIG. 10F. Referring to FIG. 10F, a spacer layer 1016 can be formed that surrounds and electrically isolates SONOS gate structures 1018. A spacer layer 1016 may include silicon dioxide. Note that in FIG. 10F, a gate mask layer 1014 has been removed by suitable process means.
While the conventional process described may produce an integrated circuit containing SONOS devices of reasonable quality and performance, certain aspects of a process may be important in maintaining device performance and/or reliability. This can be particularly true as SONOS devices are scaled to realize lower programming voltages and/or in order to maintain compatibility with CMOS process technology. Conventional SONOS-type dielectrics may suffer from certain drawbacks as SONOS-type devices are scaled down, particularly, as a thickness of an ONO dielectric within a SONOS-type device is reduced.
A drawback to conventional SONOS-type devices will now be described with reference to FIG. 9B. FIG. 9B is a side cross sectional view representation of a conventional SONOS-type device. FIG. 9B shows various portions of a SONOS device, such as those set forth in FIGS. 10A to 10F. Accordingly, like portions are referred to by the same reference characters.
FIG. 9B shows a conventional SONOS-type device in a conventional programming operation. Conventionally, an electric field can be created across an ONO dielectric (LAYERS 1004, 1006 and 1008). For example, a gate 1010 may be set to a different potential with respect to a substrate 1000. Provided such a field is large enough, charge (e.g., electrons, one of which is shown as 918) can tunnel from a substrate 1000 into one or more layers of an ONO dielectric.
A tunneling path is represented by arrows in FIG. 9B. If an ONO dielectric is sufficiently thick, charge may accumulate within a charge storing layer 1006. However, as an ONO dielectric is reduced in thickness (e.g., as devices are scaled down), in a conventional device, a majority of charge may tunnel through a middle nitride layer 1006 and accumulate at an interface between a top oxide layer 1008 and a middle nitride layer 1006. A resulting charge distribution is represented by a graph in FIG. 9B. As shown by curve 920 a majority of charge may reside an interface of layers 1006 and 1008. This is in contrast to conventional SONOS devices with a thicker ONO dielectric, in which a majority of charge may be situated closer to a substrate 1000 (within middle nitride layer 1006 and/or an interface between nitride layer 1006 and tunnel oxide layer 1004). Such a charge distribution for thicker ONO dielectric is shown by dashed lines in FIG. 9B.
Due to such a difference in charge distribution, an amount of charge and/or a programming time may not scale at the same rate as a reduction in thickness. In particular, more charge and/or a longer programming time may be needed to establish a proportional change in threshold voltage for a given smaller ONO dielectric thickness. Thinning down a conventional ONO dielectric may also degrade charge retention characteristics.
It would be desirable to provide a method of forming a dielectric layers for a SONOS-type device that may overcome the limitations noted above.
According to the present invention a method for forming a charge storing layer of a semiconductor device may include forming a first portion of a charge storing layer with a plurality of source gases introduced to a reaction chamber at a first gas flow rate ratio. At least a second portion of the charge storing layer may be formed by changing to a second gas flow rate ratio.
According to one aspect of the embodiments, a first gas flow rate ratio can be no less than 2:1 with respect to a first source gas and a second source gas.
According to another aspect of the embodiments, a second gas flow rate ratio can be less than 1:2 with respect to the first source gas and the second source gas.
According to another aspect of the embodiments, a first gas flow rate ratio can be less than 2.7:1 with respect to a first source gas and a second source gas.
According to another aspect of the embodiments, a method may further include forming at least a third portion of the charge storing layer by changing to a third gas flow rate ratio from the second gas flow rate ratio. In one particular embodiment, a third gas flow rate ratio can be essentially the same as a first gas flow rate ratio.
The present invention may also include a method of forming a charge storing dielectric that includes forming at least one charge trapping portion of a charge storing layer by switching from a first flow rate ratio of source gases to a second flow rate ratio of the source gases.
According to another aspect of the embodiments, a first and second flow rate ratio can be between a silicon source gas (Si) and at least another source gas (X). A first Si:X ratio can be less than a second Si:X ratio.
According to another aspect of the embodiments, a first and second flow rate ratio can be between a silicon source gas (SSG) and at least another source gas (X). A first SSG:X ratio can be less than a second SSG:X ratio.
According to another aspect of the embodiments, the other source gas can be a nitrogen source gas, more particularly, ammonia gas.
According to another aspect of the embodiments, forming the at least one charge trapping portion of the charge storing layer can include forming a silicon-rich charge trapping portion of a silicon oxynitride charge storing layer by switching to the second flow rate ratio.
According to another aspect of the embodiments, a charge trapping portion can have a thickness of no more than 20 angstroms.
The present invention may also include a method of forming a nonvolatile transistor. Such a method may include forming a multilayered dielectric between a tunnel dielectric and a top insulating layer by temporarily changing the rate at which a first constituent element can be introduced into a reaction chamber with respect to a second constituent element.
According to another aspect of the embodiments, a multilayered dielectric may include a silicon nitride and a first constituent element may include silicon and a second constituent element may include nitrogen.
According to another aspect of the embodiments, changing a changing the rate at which a first constituent element can be introduced includes increasing the rate at which the first constituent element can be introduced into the chamber with respect to a second constituent element.
According to another aspect of the embodiments, changing the rate at which a first constituent element can be introduced includes increasing the rate at which the first constituent element can be introduced into the chamber with respect to a second constituent element.
According to another aspect of the embodiments, a method may further include forming a top insulating layer by depositing a layer comprising silicon dioxide.
According to another aspect of the embodiments, a method may further include forming a conductive gate layer over the top insulating layer.